Field
Embodiments of the present invention generally relate to methods of patterning a metal layer, and more particularly to methods of forming an interconnection structure in an integrated cluster system without breaking vacuum in semiconductor applications.
Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors and resistors on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for faster circuits with greater circuit densities impose corresponding demands on the materials used to fabricate such integrated circuits. In particular, as the dimensions of integrated circuit components are reduced to the sub-micron scale, it is now necessary to use low resistivity conductive materials (e.g., copper) as well as low dielectric constant insulating materials (dielectric constant less than about 4) to obtain suitable electrical performance from such components.
The demands for greater integrated circuit densities also impose demands on the process sequences used in the manufacture of integrated circuit components. As the geometry limits of the structures used to form semiconductor devices are pushed against technology limits, the need for accurate pattern transfer for the manufacture of structures have small critical dimensions and high aspect ratios has become increasingly difficult. For an interconnection structure, copper is particularly advantageous for use in metal structures due to its desirable electrical properties. Copper interconnects are electrically isolated from each other by an insulating material. When the distance between adjacent metal interconnects and/or thickness of the insulating material has sub-micron dimensions, capacitive coupling may potentially occur between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit. In order to prevent capacitive coupling between adjacent metal interconnects, low dielectric constant (low k) insulating materials (e.g. dielectric constants less than about 4.0) are needed.
Copper interconnect system are typically fabricated using a damascene process in which trenches and vias are etched into dielectric layers. The trenches and vias are filled with copper which is then planarized using, for example, a chemical-mechanical planarization (CMP) process. However, several disadvantages associated with copper damascene structure have become severe concerns as feature sizes continue to decrease. For example, small feature size of the metal lines generally requires higher aspect ratio, which may adversely increase difficulty to fill such features to form void free metal structures. Forming a barrier layer within high aspect features is particularly difficult. Furthermore, as feature sizes continue to decrease, the barrier layer cannot scale, thus resulting the barrier layer in greater fraction of that particular feature. Additionally, as the feature dimensions become comparable to the bulk mean free path, the effective resistivity of copper features will increase because of non-negligible electron scattering at the copper-barrier interface and at grain boundaries.
Accordingly, an alternate metal patterning using subtractive metal etching (SME) process has recently gained wide attention. A dry plasma etching process is performed to pattern the metal materials to form one or more patterns in the interconnect structure. However, after the metal etching process, the metal interconnection is often exposed to air. Excess exposure of the metal conductive materials to air may adversely affect the nucleation capability of the metal elements to adhere to the substrate surface during a subsequently metallization process. Furthermore, poor adhesion at the interface may also result in undesired high contact resistance, thereby resulting in undesirably poor electrical properties of the device. In addition, poor nucleation of the metal elements in the back end interconnection may impact not only the electrical performance of the devices, but also on the integration of the conductive contact material subsequently formed thereon.
Recently, a metal containing passivation layer is utilized to cover the exposed surface of a metal line formed in interconnects from the dielectric bulk insulating materials. The metal containing passivation layer may minimize exposure of the metal line from the interconnect material to atmosphere/air so as to prevent damage to the semiconductor device. By utilizing this metal containing passivation layer formed on the metal line, exposure to the air/atmosphere may be minimized. However, in some cases, inadequate control of the Q-times in the processes of forming and patterning each layer, including the metal layer and passivation protection, may adversely result in excess oxidation formed onto the metal surface, thereby in high contact resistance and poor adhesion. Overly long exposure time of each layer in the interconnection structure to air or ambient may also undesirably create contamination sources or oxidation growth at the interface, resulting in film degradation and eventually leading to device failure.
Thus, there is a need for improved methods for forming an interconnection structure with improved process control without excess oxidation exposure to form accurate and desired interconnection structure for semiconductor devices.